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1. fifo-asic-physical-design fifo-asic-physical-design Public

   ASIC Physical Design of FIFO using Cadence Innovus | Floorplan → CTS → Routing → Timing & Power Analysis

   Verilog 1

2. ALU16-PPA-Optimization-OpenLane ALU16-PPA-Optimization-OpenLane Public

   RTL-to-GDSII implementation of a 16-bit ALU with PPA optimization using OpenLane (Sky130)

   Verilog 1

3. Elevator-Control-System Elevator-Control-System Public

   A Verilog HDL project for an Elevator Control System, complete with a Python Tkinter GUI for real-time simulation. 🚀

   Verilog 1

4. Signal-conditioning-90nm Signal-conditioning-90nm Public

   Design and performance analysis of analog and mixed-signal signal-conditioning blocks using 90nm CMOS technology.

   1